1. Field of the Invention
The present invention relates to an error-correction encoding and decoding system in which an information size in a block is variable and efficient error-correction encoding and decoding in a block can be attained.
2. Description of the Related Art
FIG. 1 shows an example of a code structure employed for a conventional error-correction encoder, encoding method, decoder and decoding method, as described in the article entitled "A Note on Error Correcting Code Structure for Home Use Digital VTR Using Superimposed Codes" carried in pages 27 to 32 in "Technological Research Report of the Association of Electronic Information Communication", Vol. 90, No. 28. IT 90-12 (issued on May 16, 1990).
In FIG. 1, the reference numeral 1 denotes a data block of (n.sub.1 .times.n.sub.2) which is n.sub.1 digits long in the first direction and n.sub.2 digits long in the second direction; and 2 an Ip information series of (k.sub.1 .times.k.sub.2) encoded in data block 1, which is k.sub.1 digits long in the first direction and k.sub.2 digits long in the second direction; 3 C2 check symbols each having a length of (n.sub.2 -k.sub.2) digits, which are added to Ip information series 2 when Ip information series 2 is C2-linear-encoded to a code length n.sub.2 in the second direction; 4 C1 check symbols each having a length of (n.sub.1 -k.sub.1) digits, which are added to Ip information series 2 and C2 check symbols 3 when Ip information series 2 and C2 check symbols 3 are C1-linear-encoded to a code length n.sub.1 in the first direction; 5 an Is information series which has a digit number r in the first direction smaller than the digit number (n.sub.1 -k.sub.1) of C1 check symbols and has a digit number k.sub.3 in the second direction smaller than the number of stages n.sub.2 of data block 1; 6 C3 check symbols each having a length of (n.sub.2 -k.sub.3) digits, which are added to Is information series 5 when Is information series 5 is C3-linear-encoded to a code length n.sub.2 in the second direction.
Next, the operation of the prior art system will be described. Ip information series 2 of (k.sub.1 .times.k.sub.2) digits is a product code obtained by C2-linear-encoding an information word of k.sub.1 digits to have an information length of k.sub.2 digits, a check symbol length of (n.sub.2 -k.sub.2) digits and a code length of n.sub.2 digits in the second direction and further C1-linear-encoding an information word of k.sub.2 digits to have an information length of k.sub.1 digits, a check symbol length of (n.sub.1 -k.sub.1) digits and a code length of n.sub.1 digits in the first direction.
On the other hand, in Is information series 5 of a size of (r.times.k.sub.3) digits having r digits smaller than (n.sub.1 -k.sub.1) digits in the first direction and k.sub.3 digits smaller than n.sub.2 digits in the second direction, code words each having a length of r digits are C3-linear-encoded to have an information length of k.sub.3 digits, a check symbol length of (n.sub.2 -k.sub.3) digits and a code length of n.sub.2 digits in the second direction.
The data C3-linear-encoded is added to (superimposed on) a part of C1 check symbols C1-linear-encoded, which is shown as a hatched area in FIG. 1, on the finite body. Thus, data block 1 of (n.sub.1 .times.n.sub.2) digits is formed to contain Ip information series 2 and Is information series 5.
Next, a decoding operation will be described. A received data block having a size of (n.sub.1 .times.n.sub.2) digits containing the superimposing data is C1-decoded. Then, C3 codes superimposing on the hatched portion of C1 check symbols 4 are separated. In this superimposition-separation, an elimination flag is set in the hatched portion of the check symbols 4 and elimination is corrected during C1 decoding.
The size of an obtained elimination error at the eliminated position is superimposition-separated as C3 code data, and, at the same time, digit error correction is executed through error correction on data which have not superimposed on. If elimination cannot be corrected during C1 decoding, a flag is set indicating that correction is impossible.
Ip information series 2 of (k.sub.1 .times.k.sub.2) digits is decoded by executing elimination-correction in C2 decoding using the correction-impossible flag of C1 decoding. The received C3 code words of the Is information series of (r.times.k.sub.3) digits is decoded by executing elimination-correction in C3 decoding using the correction-impossible flag of C1 decoding.
Consequently, if an information size is within the size of Ip information series 2, product codes of (n.sub.1 .times.n.sub.2) digits are formed to include C1 codes and C2 codes. If an information size is larger than the size of the Ip information series, C3 codes are formed as Is information series 5 to superimpose on the product codes, thereby increasing an information amount. The code structure of FIG. 1 is therefor effective for error correction.
Since conventional encoder, encoding method, decoder and decoding method are such as described above, when Is information series 5 is added, encoding requires an arithmetic operation to superimpose C3 codes and decoding requires an arithmetic operation to superimposition-separate C3 codes. However, the amount of operations is large. In decoding C3 codes, since C3 codes are superimposition-separated from C1 codes, an increase in number of error digits of C1 codes makes the superimposition-separation and the decoding of C3 codes impossible. Furthermore, C3 decoding can be initiated only after the superimposition-separation executed in decoding C1 codes, resulting in much time to decode an entire block.